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EM73962A 4-BIT MICROCONTROLLER
GENERAL DESCRIPTION
EM73962A is an advanced single chip CMOS 4-bit micro-controller. It contains 16K-byte ROM, 372-nibble RAM, 4-bit ALU, 13-level subroutine nesting, 22-stage time base, two 12-bit timer/counters for the kernal function. EM73962A also contains 5 interrupt sources, 3 I/O ports (including 1 input port and 2 bidirection ports), LCD display (40x8), built-in sound generator. Except low-power consumption and high speed, EM73962A also have a sleep mode for power saving function. EM73962A is suitable for appliaction in many fields, for example : family appliance, consumer products, hand held games and the toy controller ... etc.
FEATURES
* Operation voltage * Clock source * * * * * * * * * * * : 2.4V to 5.0V. : Single clock system using RC. oscillator. External clock and internal clock is available by mask option. Oscillation frequency : 480K, 1M, 2M and 4M Hz is available by mask option. Instruction set : 107 powerful instructions. Instruction cycle time : Up to 2us for 4 MHz. ROM capacity : 16384 X 8 bits. RAM capacity : 372 X 4 bits. Input port : 1 port (P0.0-P0.3) and sleep/hold releasing function are available by mask option. (each input pin is pull-up and pull-down resistor available by mask option). Bidirection port : 1 port (P8). P8(0..3) and sleep/hold releasing function are available by mask option. 12-bit timer/counter : Two 12-bit timer/counters are programmable for timer, event counter and pulse width measurement. Built-in time base counter : 22 stages. Subroutine nesting : Up to 13 levels. Interrupt : External . . . . . 2 input interrupt sources. Internal . . . . . . 2 Timer overflow interrupts. 1 Time base interrupt. LCD driver : 40 X 8 dots, 1/8 duty, LCD bias is 1/4 and 1/5 available by mask option, LCD bias resistor is 20K X 5 and 10K X 5 available by mask option. Sound effect : Tone generator, random generator and volume control. Power saving function: Sleep mode and Hold mode. Package type : EM73962AH Chip form 62 pins.
* * * *
* This specification are subject to be changed without notice.
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EM73962A 4-BIT MICROCONTROLLER
FUNCTION BLOCK DIAGRAM
RESET CLK
Reset Control
Clock Generator
Timing Generator
Sleep Mode Control
System Control Data pointer Interrupt Control Time Base Instruction Decoder Instruction Register ACC Stack pointer Stack ROM S HR LR P0.0/WAKEUP0 P0.1/WAKEUP1 P0.2/WAKEUP2 P0.3/WAKEUP3
Data Bus
ALU Flag Z C
ROM Timer/Counter (TA,TB) PC
I/O Control LCD Driver SOUND GEN.
COM0~COM7
SEG0~SEG39
SOUND
P8.1(TRGB)/WAKEUPB
PIN DESCRIPTIONS
Symbol V DD Vss RESET Pin-type Function Power supply (+) Power supply (-) System reset input signal, low active mask option : none pull-up RC or external clock source connecting pin 4-bit input port with Sleep/Hold releasing function mask option : wakeup enable, pull-up wakeup enable, none wakeup disable, pull-up wakeup disable, pull-down wakeup disable, none 2-bit bidirection I/O port with external interrupt sources input and Sleep /Hold releasing function mask option : wakeup enable, push-pull wakeup disable, push-pull wakeup disable, open-drain 2-bit bidirection I/O port with time/counter A,B external input and Sleep /Hold releasing function mask option : wakeup enable, push-pull wakeup disable, push-pull wakeup disable, open-drain Built-in sound effect output LCD common output pins LCD segment output pins No connecting for COB
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RESET-A
CLK P0.(0..3)/WAKEUP0..3
OSC-C INPUT-B
P8.0(INT1)/WAKEUPA I/O-L P8.2(INT0)/WAKEUPC
P8.1(TRGB)/WAKEUPB I/O-L P8.3(TRGA)/WAKEUPD
SOUND COM0~COM7 SEG0~SEG39 TEST
* This specification are subject to be changed without notice.
P8.3(TRGA)/WAKEUPD
P8.0(INT1)/WAKEUPA
P8.2(INT0)/WAKEUPC
EM73962A 4-BIT MICROCONTROLLER
FUNCTION DESCRIPTIONS
PROGRAM ROM ( 16K X 8 bits ) for EM73962A 16 K x 8 bits program ROM contains user's program and some fixed data. The basic structure of program ROM can be divided into 4 parts. 1. Address 0000h: Reset start address. 2. Address 0002h - 000Ch : 5 kinds of interrupt service routine entry addresses. 3. Address 000Eh - 0086h : SCALL subroutine entry address, only available at 000Eh, 0016h, 001Eh, 0026h, 002Eh, 0036h, 003Eh, 0046h, 004Eh, 0056h, 005Eh, 0066h, 006Eh, 0076h, 007Eh, 0086h. 4. Address 0000h - 07FFh : LCALL subroutine entry address. 5. Address 0000h - 1FFFh : Except used as above function, the other region can be used as user's program region. address 0000h 0002h 0004h 0006h 0008h 000Ah 000Ch 000Eh 0086h : : 07FFh 0800h 0FFFh 1000h Bank 1 1FFFh Bank 2 Bank 3
Data table for [LDAX],[LDAXI] instruction
Bank 0 : Reset start address INT0; interrupt service routine entry address TRGA TRGB TBI INT1
SCALL, subroutine call entry address
Subroutine call entry address designated by [LCALL a] instruction
* This specification are subject to be changed without notice.
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EM73962A 4-BIT MICROCONTROLLER
User's program and fixed data are stored in the program ROM. User's program is according the PC value to send next executed instruction code. The 16Kx8 bits program ROM can be divided into 4 banks. There are 4Kx8 bits in each bank. The bank of the program ROM is selected by P3(1..0). The program counter is a 13-bit binary counter. The PC and P3 are initialized to "0" during reset. When P3(1..0)=00B, the bank0 and bank1 of program ROM will be selected. P3(1..0)=01B, the the bank0 and bank2 will be selected. P3(1..0)=01B, the bank0 and bank3 will be selected. Address 0000h : : 0FFFh 1000h : : 1FFFh P3=xx00B P3=xx01B P3=xx10b
Bank0
Bank0
Bank0
Bank1
Bank2
Bank3
PROGRAM EXAMPLE:
BANK : : : LDIA OUTA B : XA : : : LDIA OUTA B : XB : : : LDIA OUTA B : XC : : : B XD : : : : ;--------------BANK XA1 : : : B : XA2 : : START: 0
#00H P3 XA1
; set program ROM to bank1
#01H P3 XB1
; set program ROM to bank2
#02H P3 XC1
; set program ROM to bank3
XD
-------------------- -------------------- -------------------- 1
XA
* This specification are subject to be changed without notice.
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EM73962A 4-BIT MICROCONTROLLER
B XA2 : ;--------------- -------------------- -------------------- -------------------- -BANK 2 XB1 : : : B XB : XB2 : : B XB2 : ;--------------- -------------------- -------------------- -------------------- -BANK 3 XC1 : : : B XC : XC2 : : B XC2
Fixed data can be read out by table-look-up instruction. Table-look-up instruction is depended on the Data Pointer (DP) to ROM address, then to get the ROM code data : LDAX LDAXI Acc ROM[DP]L Acc ROM[DP]H,DP+1
DP is a 12-bit data register which can store the program ROM address to be the pointer for the ROM code data. First, user load ROM address into DP by instruction "STADPL, STADPM, STADPH", then user can get the lower nibble of ROM code data by instruction "LDAX" and higher nibble by instruction "LDAXI" PROGRAM EXAMPLE: Read out the ROM code of address 1777h by table-look-up instruction.
LDIA #07h; STADPL STADPM STADPH : LDL #00h; LDH #03h; LDAX STAMI LDAXI STAM ; ORG 1777h DATA 56h; ; [DP]L 07h ; [DP]M 07h ; [DP]H 07h, Load DP=777h
; ACC 6h ; RAM[30] 6h ; ACC 5h ; RAM[31] 5h
DATA RAM ( 372-nibble ) There is total 372 - nibble data RAM from address 000 to 17Fh Data RAM includes 3 parts: zero page region, stacks and data area.
* This specification are subject to be changed without notice.
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EM73962A 4-BIT MICROCONTROLLER
Increment Address Bank 0 000h - 00Fh 010h - 01Fh 020h - 02Fh
: : :
Zero-page
Increment
0C0h - 0CFh 0D0h - 0DFh 0E0h - 0EFh 0F0h - 0F3h
Level 0 Level 4 Level 8 Level 12
Level 1 Level 5 Level 9
Level 2 Level 6 Level 10
Level 3 Level 7 Level 11
Bank 1
100h - 10Fh 110h - 11Fh
: : :
160h - 16Fh 170h - 17Fh
ZERO- PAGE: From 000h to 00Fh is the location of zero-page. It is used as the pointer in zero -page addressing mode for the instruction of "STD #k,y; ADD #k,y; CLR y,b; CMP k,y". PROGRAM EXAMPLE: To wirte immediate data "07h" to address "003h" of RAM and to clear bit 2 of RAM.
STD #07h, 03h ; RAM[03] 07h CLR 0Eh,2 ; RAM[0Eh]2 0
STACK: There are 13 - level (maximum) stack for user using for subroutine (including interrupt and CALL). User can assign any level be the starting stack by giving the level number to stack pointer(SP). When user using any instruction of CALL or subroutine, before entry the subroutine, the previous PC address will be saved into stack until return from those subroutines, the PC value will be restored by the data saved in stack. DATA AREA: Except the special area used by user, the whole RAM can be used as data area for storing and loading general data. ADDRESSING MODE The 372 nibble data memory consists of two banks (bank 0 and bank 1). There are 244x4 bits (address 000h~0F3h) on bank 0 and 128x4 bits (address 100h~17Fh) on bank 1.
* This specification are subject to be changed without notice.
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EM73962A 4-BIT MICROCONTROLLER
There are three addressing modes in the data memory : (1) Indirect addressing mode: The bank is selected by P9.3. When P9.3 is cleared to "0", the bank 0 is selected. When P9.3 is set to "1", the bank 1 is selected. The address in the bank are specified by the HL registers.
P9.3 HR LR
RAM address
PROGRAM EXAMPLE: Load the data of RAM address "143h" to RAM address "023h".
SEP P9,3 LDL #3h LDH #4h LDAM CLP P9,3 LDL #2h LDH #3h STAM ; P9.3 1 ; LR 3 ; HR 4 ; Acc RAM[134h] ; P9.3 0 ; LR 2 ; HR 3 ; RAM[023h] Acc
(2) Direct addressing mode: The bank is selected by P9.3. When P9.3 is cleared to "0", the bank 0 is selected. When P9.3 is set to "1", the bank 1 is selected. The address in the bank are directly specified by 8 bits of the second byte in the instruction field.
instruction field xxxxxxxx P9.3
RAM address
SEP P9,3 LDA 43h CLP P9,3 STA 23h ; P9.3 1 ; Acc RAM[134h] ; P9.3 0 ; RAM[023h] Acc
xxxxxxxx
PROGRAM EXAMPLE: Load the data of RAM address "143h" to RAM address "023h".
(3) Zero-page addressing mode: The zero-page is the bank 0 (address 000h~00Fh). The address are the lower 4 bits of the second byte in the instruction field.
instruction field yyyy
RAM address 0
0000 yyyy
PROGRAM EXAMPLE: Write immediate "0Fh" to RAM address "005h".
STD #0Fh, 05h ; RAM[05h] 0Fh
* This specification are subject to be changed without notice.
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EM73962A 4-BIT MICROCONTROLLER
PROGRAM COUNTER (16K ROM) for EM73962A Program counter ( PC ) is composed by a 13-bit counter, which indicates the next executed address for the instruction of program ROM. For a 8K - byte size ROM, PC can indicate address form 0000h - 1FFFh, for BRANCH and CALL instrcutions, PC is changed by instruction indicating. (1) Branch instruction: SBR a Object code: 00aa aaaa Condition: SF=1; PC PC 12-6.a ( branch condition satisified ) PC Hold original PC value+1 a a a a a a
SF=0; PC PC +1( branch condition not satisified ) PC Original PC value + 1
LBR a Object code: 1100 aaaa aaaa aaaa Condition: SF=1; PC PC 12.a ( branch condition satisified ) PC
Hold
+2
a
a
a
a
a
aa
a
a
a
a
a
SF=0; PC PC +2( branch condition not satisified ) PC Original PC value + 2
SLBR a Object code: 0101 0101 1100 aaaa aaaa aaaa (a:1000h~1FFFh) 0101 0111 1100 aaaa aaaa aaaa (a:0000h~0FFFh) Condition: SF=1; PC a ( branch condition satisified) PC a a a a a a a a a a a a a
SF=0 ; PC PC + 3 ( branch condition not satisified ) PC Original PC value + 3
(2) Subroutine instruction: SCALL a Object code: 1110 nnnn Condition : PC a ; a=8n+6 ; n=1..Fh ; a=86h, n=0 PC 0 0 0 0 0 a a a a a 1 1 0
LCALL a Object code: 0100 0aaa aaaa aaaa Condition: PC a * This specification are subject to be changed without notice.
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EM73962A 4-BIT MICROCONTROLLER
PC 0
0
a
a
a
a
a
a
a
a
a
a
a
RET Object code: 0100 1111 Condition: PC STACK[SP]; SP + 1 PC The return address stored in stack
RT I Object code: 0100 1101 Condition : FLAG. PC STACK[SP]; EI 1; SP + 1 PC The return address stored in stack
(3) Interrupt acceptance operation: When an interrupt is accepted, the original PC is pushed into stack and interrupt vector will be loaded into PC,The interrupt vectors are as following: INT0 (External interrupt from P8.2) PC 0 0 0 0 0 0 0 0 0 0 0 1 0
TRGA (Timer A overflow interrupt) PC 0 0 0 0 0 0 0 0 0 0 1 1 0
TRGB (Time B overflow interrupt) PC 0 0 0 0 0 0 0 0 01 0 00
TBI (Time base interrupt) PC 0 0 0 0 0 0 0 0 01 0 10
INT1 (External interrupt from P8.0) PC 0 (4) Reset operation: PC 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 01 1 00
(5) Other operations: For 1-byte instruction execution: PC + 1 For 2-byte instruction execution: PC + 2 For 3-byte instruction execution: PC + 3
* This specification are subject to be changed without notice.
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EM73962A 4-BIT MICROCONTROLLER
ACCUMULATOR Accumulator is a 4-bit data register for temporary data. For the arithematic, logic and comparative opertion .., ACC plays a role which holds the source data and result. FLAGS There are three kinds of flag, CF ( Carry flag ), ZF ( Zero flag ), SF ( Status flag ), these 3 1-bit flags are affected by the arithematic, logic and comparative .... operation. All flags will be put into stack when an interrupt subroutine is served, and the flags will be restored after RTI instruction executed. (1) Carry Flag ( CF ) The carry flag is affected by following operation: a. Addition : CF as a carry out indicator, when the addition operation has a carry-out, CF will be "1", in another word, if the operation has no carry-out, CF will be "0". b. Subtraction : CF as a borrow-in indicator, when the subtraction operation must has a borrow, in the CF will be "0", in another word, if no borrow-in, CF will be "1". c. Comparision: CF is as a borrow-in indicator for Comparision operation as the same as subtraction operation. d. Rotation: CF shifts into the empty bit of accumulator for the rotation and holds the shift out data after rotation. e. CF test instruction : For TFCFC instruction, the content of CF sends into SF then clear itself "0". For TTSFC instruction, the content of CF sends into SF then set itself "1". (2) Zero Flag ( ZF ) ZF is affected by the result of ALU, if the ALU operation generate a "0" result, the ZF will be "1", otherwise, the ZF will be "0". (3) Status Flag ( SF ) The SF is affected by instruction operation and system status. a. SF is initiated to "1" for reset condition. b. Branch instruction is decided by SF, when SF=1, branch condition will be satisified, otherwise, branch condition will not be satisified by SF = 0. PROGRAM EXAMPLE: Check following arithematic operation for CF, ZF, SF
LDIA #00h; LDIA #03h; ADDA #05h; ADDA #0Dh; ADDA #0Eh; CF ZF 1 0 0 0 0 SF 1 1 1 0 0 10.8.2001 10
* This specification are subject to be changed without notice.
EM73962A 4-BIT MICROCONTROLLER
ALU The arithematic operation of 4 - bit data is performed in ALU unit. There are 2 flags can be affected by the result of ALU operation, ZF and SF. The operation of ALU can be affected by CF only. ALU STRUCTURE ALU supported user arithematic operation function, including : addition, subtraction and rotaion.
DATA BUS
ALU
ZF CF SF
ALU FUNCTION (1) Addition: For instruction ADDAM, ADCAM, ADDM #k, ADD #k,y .... ALU supports addition function. The addition operation can affect CF and ZF. For addition operation, if the result is "0", ZF will be "1", otherwise, not equal "0", ZF will be "0", When the addition operation has a carry-out. CF will be "1", otherwise, CF will be "0". EXAMPLE:
Operation 3+4=7 7+F=6 0+0=0 8+8=0 Carry 0 1 0 1 Zero 0 0 1 1
(2) Subtraction: For instruction SUBM #k, SUBA #k, SBCAM, DECM... ALU supports user subtraction function. The subtraction operation can affect CF and ZF, For subtraction operation, if the result is negative, CF will be "0", it means a borrow out, otherwise, if the result is positive, CF will be "1". For ZF, if the result of subtraction operation is "0", the ZF will be "1", otherwise, ZF will be "1". EXAMPLE:
Operation 8-4=4 7-F=-8(1000) 9-9=0 Carry 1 0 1 Zero 0 0 1 10.8.2001 11
* This specification are subject to be changed without notice.
EM73962A 4-BIT MICROCONTROLLER
(3) Rotation: There are two kinds of rotation operation, one is rotation left, the other is rotation right. RLCA instruction rotates Acc value to left, shift the CF value into the LSB bit of Acc and the shift out data will be hold in CF.
MSB LSB ACC CF
RRCA instruction operation rotates Acc value to right, shift the CF value into the MSB bit of Acc and the shift out data will be hold in CF.
MSB LSB ACC CF
PROGRAM EXAMPLE: To rotate Acc right and shift a "1" into the MSB bit of Acc.
TTCFS; CF 1 RRCA; rotate Acc right and shift CF=1 into MSB.
HL REGISTER HL register are two 4-bit registers, they are used as a pair of pointer for the address of RAM memory and also 2 independent temporary 4-bit data registers. For some instruction, L register can be a pointer to indicate the pin number ( Port4 ). HL REGISTER STRUCTURE
3
2
1
0
3
2
1
0
H REGISTER L REGISTER
HL REGISTER FUNCTION (1) For instruction : LDL #k, LDH #k, THA, THL, INCL, DECL, EXAL, EXAH, HL register used as a temporary register. PROGRAM EXAMPLE: Load immediate data "5h" into L register, "Dh" into H register.
LDL #05h; LDH #0Dh;
(2) For instruction LDAM, STAM, STAMI .., HL register used as a pointer for the address of RAM memory. PROGRAM EXAMPLE: Store immediate data #Ah into RAM of address 35h.
* This specification are subject to be changed without notice.
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LDL #5h; LDH #3h; STDMI #0Ah; RAM[35] Ah
(3) For instruction : SELP, CLPL, TFPL, L regieter be a pointer to indicate the bit of I/O port. When LR = 0 indicate P4.0 PROGRAM EXAMPLE: To set bit 0 of Port4 to "1"
LDL #00h; SEPL ; P4.0 1
STACK POINTER (SP) Stack pointer is a 4-bit register which stores the present stack level number. Before using stack, user must set the SP value first, CPU will not initiate the SP value after reset condition. When a new subroutine is accepted, the SP will be decreased one automatically, in another word, if returning from a subroutine, the SP will be increased one. The data transfer between ACC and SP is by instruction of "LDASP" and "STASP". DATA POINTER (DP) Data pointer is a 12-bit register which stores the address of ROM can indicate the ROM code data specified by user (refer to data ROM). CLOCK AND TIMING GENERATOR The clock generator is supported by a single clock system, the clock source comes from RC oscillation, the working frequency range is 480 K Hz to 4 MHz depending on the external resistor. CLOCK AND TIMING GENERATOR STRUCTURE The clock generator connects outside compoments ( only a resistor connects to VDD and CLK pin). The clock generator generates a basic system clock "fc". When CPU sleeping, the clock generator will be stoped until the sleep condition released. The system clock control generates 4 basic phase signals ( S1, S2, S3, S4 ) and system clock.
sleep
fc
CLK
Clock generator
System clock control
System clock
CLK
S1
S2
S3
S4
RC connection
CLOCK AND TIMING GENERATOR FUNCTION The frequency of fc is the oscillation frequency for CLK by RC oscillator.
* This specification are subject to be changed without notice.
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The instruction cycle equal 8 basic clock fc. 1 instruction cycle = 8 / fc TIMING GENERATOR AND TIME BASE The timing generator produces the system clock from basic clock pulse which can be normal mode or slow mode clock. 1 instruction cycle = 8 basic clock pulses There are 22 stages time base.
Prescaler Binary counter 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
fc
123
When working in the single clock mode, the timebase clock source is come from fc. Time base provides basic frequency for following function: 1. TBI (time base interrupt). 2. Timer/counter, internal clock source. 3. Warm-up time for sleep - mode releasing. TIME BASE INTERRUPT (TBI ) The time base can be used to generate a fixed frequency interrupt. There are 8 kinds of frequencies can be selected by setting "P25"
Single clock mode P25 3 2 1 0 ( initial value 0000 ) 0 0 x x: Interrupt disable 0 1 0 0: Interrupt frequency fc / 210 Hz 0 1 0 1: Interrupt frequency fc / 211 Hz 0 1 1 0: Interrupt frequency fc / 212 Hz 0 1 1 1: Interrupt frequency fc / 213 Hz 1 1 0 0: Interrupt frequency fc / 29 Hz 1 1 0 1: Interrupt frequency fc / 28 Hz 1 1 1 0: Interrupt frequency fc / 215 Hz 1 1 1 1: Interrupt frequency fc / 217 Hz 1 0 x x: Reserved
TIMER / COUNTER ( TIMERA, TIMERB) Timer/counters can support user three special functions: 1. Even counter 2. Timer. 3. Pulse-width measurement. These three functions can be executed by 2 timer/counter independently. For timerA, the counter data is saved in timer register TAH, TAM, TAL, which user can set counter initial value and read the counter value by instruction "LDATAH(M,L), STATAH(M,L)" and timer register is TBH, TBM, TBL and W/R instruction "LDATBH (M,L), STATBH (M,L)".
* This specification are subject to be changed without notice.
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The basic structure of timer/counter is composed by two same structure counter, these two counters can be set initial value and send counter value to timer register, P28 and P29 are the command ports for timerA and timer B, user can choose different operation mode and different internal clock rate by setting these two ports. When timer/counter overflow, it will generate a TRGA(B) interrupt request to interrupt control unit.
INTERRUPT CONTROL TRGA request DATA BUS
12 BIT COUNTER 12 BIT COUNTER
TRGB request
P8.3/ TRGA internal clock
EVENT COUNTER CONTROL TIMER CONTROL PULSE-WIDTH MEASUREMENT CONTROL
EVENT COUNTER CONTROL TIMER CONTROL PULSE-WIDTH MEASUREMENT CONTROL
P8.1/ TRGB
internal clock
P28
TMSA
IPSA
P29
TMSB
IPSB
TIMER/COUNTER CONTROL P8.1/TRGB, P8.3/TRGA are the external timer inputs for timerB and timerA, they are used in event counter and pulse-width measurement mode. Timer/counter command port: P28 is the command port for timer/counterA and P29 is for the timer/ counterB. Port 28 3210 TMSA IPSA Initial state : 0000 Timer/Counter mode selection TMSA(B) Function description 00 Stop 01 Event counter mode 10 Timer mode 11 Pulse width measurement mode Internal Pulse-rate selection IPSA(B) Function description 00 fc/210Hz 01 fc/214Hz 10 fc/218Hz 11 fc/222Hz
Port 29
3210 TMSB IPSB Initial state : 0000
* This specification are subject to be changed without notice.
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EM73962A 4-BIT MICROCONTROLLER
TIMER/COUNTER FUNCTION Timer/counterA can be programmable for timer, event counter and pulse width measurement. Each timer/ counter can execute any one of these functions independly. EVENT COUNTER MODE For event counter mode, timer/counter increases one at any rising edge of P8.1/TRGB for timerB (P8.3/ TRGA for timer A). When timerB (timerA) counts overflow, it will give interrupt control an interrupt request TRGB (TRGA).
P8.1/TRGB (P8.3/TRGA)
TimerB (TimerA) value n
n+1
n+2
n+3
n+4
n+5
n+6
PROGRAM EXAMPLE: Enable timerA with P28
LDIA #0100B; OUTA P28; Enable timerA with event counter mode
TIMER MODE For timer mode ,timer/counter increase one at any rising edge of internal pulse. User can choose 4 kinds of internal pulse rate by setting IPSB for timerB (IPSA for timerA). When timer/counter counts overflow, TRGB (TRGA) will be generated to interrupt control unit.
Internal pulse
TimerB (TimerA )value
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
PROGRAM EXAMPLE: To generate TRGA interrupt request after 60 ms with system clock fc=4MHz
LDIA EXAE EICIL LDIA STATAL LDIA STATAM LDIA STATAH LDIA OUTA #0100B 110111B #06H #01H #0FH #1000B P28 ; ; enable mask 2 ; interrupt latch 0, enable EI ; ; ; ; ; ; ; ; enable timerA with internal pulse rate: fc/210 Hz
NOTE:
The preset value of timer/counter register is calculated as following procedure. Internal pulse rate: fc/210 ; fc = 4MHz The time of timer counter count one = 210 /fc = 1024/4000=0.256ms The number of internal pulse to get timer overflow = 60 ms/ 0.256ms = 234.375 = 0EAH The preset value of timer/counter register = 1000H - 0EAH = 0F16H
PULSE WIDTH MEASUREMENT MODE
* This specification are subject to be changed without notice.
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For the pulse width measurement mode, the counter only incresed by the rising edge of internal pulse rate as external timer/counter input (P8.1/TRGB, P8.3/TRGA ), interrupt request will be generated as soon as timer/counter count overflow.
P8.1/TRGB(P8.3/TRGA)
Internal pulse
TimerB(TimerA) value
n
n+1
n+2
n+3
n+4
n+5
PROGRAM EXAMPLE: Enable timerA by pulse width measurement mode.
LDIA OUTA #1100b P28 ; ; Enable timerA with pulse width measurement mode.
INTERRUPT FUNCTION There are 5 interrupt sources, 2 external interrupt sources, 3 internal interrupt sources. Multiple interrupts are admitted according the priority.
Type Interrupt source Priority Interrupt Latch IL5 IL4 IL3 IL2 IL1 IL0 Interrupt Enablecondition EI=1 EI=1,MASK3=1 EI=1,MASK2=1 EI=1,MASK1=1 EI=1,MASK0=1 ProgramROM entry address 002h 004h 006h 008h 00Ah 00Ch
External Internal Internal Internal Internal External
Externalinterrupt(INT0) Reserved TimerA overflow interrupt (TRGA) TimerB overflow interrupt (TRGB) Time base interrupt(TBI) Externalinterrupt(INT1)
1 2 3 4 5 6
INTERRUPT STRUCTURE
MASK0 MASK1 MASK1 MASK2 MASK3 INT1 r0 Reset by system reset and program instruction IL0 TBI r1 IL1 TRGB r2 IL2 TRGA r3 IL3 r4 IL4 INT0 r5 IL5
Priority checker Reset by system reset and program instruction Set by program instruction EI Entry address generator
Interrupt request
Interrupt entry address
Interrupt controller: IL0-IL5 : Interrupt latch. Hold all interrupt requests from all interrupt sources. ILr can not be set by program, but can be reset by program or system reset, so IL only can decide which interrupt source can be accepted. : Except INT0 ,MASK register can promit or inhibit all interrupt sources.
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MASK0-MASK3
* This specification are subject to be changed without notice.
EM73962A 4-BIT MICROCONTROLLER
EI : Enable interrupt Flip-Flop can promit or inhibit all interrupt sources, when interrupt happened, EI is cleared to "0" automatically, after RTI instruction happened, EI will be set to "1" again. : Check interrupt priority when multiple interrupts happened.
Priority checker
INTERRUPT FUNCTION The procedure of interrupt operation: 1. Push PC and all flags to stack. 2. Set interrupt entry address into PC. 3. Set SF= 1. 4. Clear EI to inhibit other interrupts happened. 5. Clear the IL for which interrupt source has already be accepted. 6. To excute interrupt subroutine from the interrupt entry address. 7. CPU accept RTI, restore PC and flags from stack. Set EI to accept other interrupt requests. PROGRAM EXAMPLE: To enable interrupt of "INT0, TRGA"
LDIA EXAE EICIL #1100B; ; set mask register "1100B" 111111B ; enable interrupt F.F.
POWER SAVING FUNCTION ( Sleep / Hold functlon ) During sleep and hold condition, CPU holds the system's internal status with a low power consumption, for the sleep mode, the system clock will be stoped in the sleep condition and system need a warm up time for the stability of system clock running after wakeup. In the other way, for the hold mode, the system clock does not stop at all and it does not need a warm-up time any way. The sleep and hold mode is controlled by Port 16 and released by P0(0..3)/WAKEUP0..3 or P8(0..3)/ WAKEUPA..D. P16 3210
WM SE SWWT
initial value :0000
WM Set wake-up release mode 0 1 Wake-up in edge release mode Wake-up in level release mode
SWWT Set wake-up warm-up time
00 01 10 11 2 18 / fc 2 14 / fc 2 16 / fc Hold mode SE Enable sleep/hold 0 Reserved 1 Enable sleep / hold rnode
Sleep and hold condition: 1. Osc stop ( sleep only ) and CPU internal status held. 2. Internal time base clear to "0". 3. CPU internal memory, flags, register, I/O held original states. 4. Program counter hold the executed address after sleep release. Release condition: 1. Osc start to oscillating.(sleep only). 2. Warm-up time passing (sleep only). 3. According PC to execute the following program.
* This specification are subject to be changed without notice.
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EM73962A 4-BIT MICROCONTROLLER
There is one kind of sleep/hold release mode. Edge release mode: Release sleep/hold condition by the falling edge of any one of P0(0..3)/WAKEUP0..3 or P8(0..3)/ WAKEUPA..D. Note : There are 8 independent mask options for wakeup function in EM73962A. So, the wakeup function of P0(0..3)/WAKEUP0..3 and P8(0..3)/WAKEUPA..D are enabled or disabled independently. LCD DRIVER It can directly drive the liquid crystal display ( LCD ) and has 40 segments, 8 commons output pins. There are total 40x8 dots can be display. (1) LCD driver control command register: Port27 3 2 1 0 Initial value: 0h LDC * * LCD DISPLAY CONTROL LDC Function description 00 LCD display disable 01 Blanking, change COMMON pin output 10 Reserved 11 LCD display enable * : Don't care. P27 is the LDC driver control command register . The initial value is 0000. When LDC ( bit2 and bit3 of P27 ) is set to "00", the LCD display is disabled. When LDC is set to "01", the LCD is blanking, the COM pins are inactive and the SEG pins continuously output the display data. The power switch of LCD driver is turned off when the CPU is reseted. When LDC is set to "11", the LCD display is enabled, the power switch is turned on and it can not be turned off forever except the CPU is reseted again. The power switch is also turned off during the sleep operation. Users must enable the LCD display again by self when the CPU is waked up. (2) LCD display data area: The LCD display data is stored in the display data area of the data memory (RAM). The display data area begins with address 20H during reset. The LCD display data area is as below:
RAM 20H 30H 40H 50H 60H 70H 80H 90H 0 1 2 3 4 5 6 7 8 9 A B C D E F
COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7
SSSS SSSS SS SS SSSS SSSS SSS S SSSS SSSS EEEE EEEE EE EE EEEE EEEE EEE E EEEE EEEE GGGG GGGG GG GG GGGG GGGG GGG G GGGG GGGG 0123 4567 89 11 1111 1111 222 2 2222 2233 01 2345 6789 012 3 4567 8901 SSSS SSSS EEEE EEEE GGGG GGGG 3333 3333 2345 6789
b bb b i ii i t tt t 0 12 3
* This specification are subject to be changed without notice.
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EM73962A 4-BIT MICROCONTROLLER
Read automatically the display data from the display data area and send to the LCD driver by the hardware. Therefore, the display patterns can be changed only by overwritting the contents of the display data area with the software. The data memory which is not used to store the LCD display data and the addresses are not connected to the LCD can be used to store the ordinary user's processing data. PROGRAM EXAMPLE: LDIA #1100B ; LCD display enable OUTA P27 LDIA #1010B STA 24H (3) LCD waveform : (1/5 bias)
(3) LCD waveform : S E G 0
* TYPE A, modify 1/4 bias :
COM0
VDD
V4 V3 V2 V1 VSS
* TYPE B, modify 1/4 bias :
COM0
VDD
V4 V3 V2 V1 VSS
COM0
: ON : OFF
COM1 COM7
COM1
BIAS VDD / VDD V4 / VDD V3 / VDD V2 / VDD V1 / VDD VSS = 0
Modify 1/4 1 17/23 12/23 11/23 6/23 0
1/4 1
SEG0
SEG0
3/4 1/2
SEG0-COM0
SEG0-COM0
ON
1/4 0
ON
SEG0-COM1
SEG0-COM1
OFF
OFF
Frame freq. =65Hz
Frame freq.=65Hz
* TYPE A, 1/4 bias :
COM0
VDD
V3 V2 V1 VSS
* TYPE B, 1/4 bias :
COM0
VDD
V3 V2 V1 VSS
COM1
COM1
SEG0
COM1
SEG0-COM0 ON
SEG0-COM0 ON
SEG0-COM0 OFF
Frame freq.=65Hz
SEG0-COM1 ON
Frame freq. =65Hz
* This specification are subject to be changed without notice.
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EM73962A 4-BIT MICROCONTROLLER
SOUND EFFECT EM73962A has a built-in sound generator. It includes the tone generator, random generator and volume control. The tone generator is a binary down counter and the random generator is a 9-bit linear feedback shift register. When the CPU is reseted or sleeping, the sound generator is disabled and the output pin (SOUND) is low.
P.30 P23,P24 fb
3 kinds f1 Tone generator of divider
/2
/2 Output control SOUND PWM
f2x2
Random generator
Low
P17
volume control
Sound generator command register There are 3 kinds of basic frequency for sound generator which can be selected by P30. The output of sound effect is tone and random combination. Port30
3 2 BFREQ 1 0 SMODE Initial value : 0000
BFREQ 00 01 10 11
Basic frequency (f1) select 240 KHz 120 KHz 60 KHz don't care
SMODE 00 01 10 11
Sound generator mode Disable Tone output Random output Tone+random output
Tone frequency register The 8-bit tone frequency register is P24 and P23. The tone frequency will be changed when user output the different data to P23. Thus, the data must be output to P24 before P23 when user want to change the 8-bit tone frequency (TF). Port24 Port23
3 2 1 0 3 2 1 0 Initial value : 1111 1111 Higher nibble register Lower nibble register
** f1=240K/2X, f2=f1/(TF+1)/2, TF=1~255, TF0 ** Example : BFREQ=10, TF=00110001B. f1=60K Hz, f2=60K Hz/50/2=600 Hz Random generator f(x)=x9+x4+1
1 2 3
+
4 5 6 7 8 9
* This specification are subject to be changed without notice.
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EM73962A 4-BIT MICROCONTROLLER
Volume control register The are 8 levels of volume for sound generator. P17 is the volume control register. Port17 Initial value : * 1111 3 2 1 0 * VCR VCR ts/tp 1 1 1 8/8 ts 1 1 0 7/8 1 0 1 6/7 1 0 0 5/8 0 1 1 4/8 tp 0 1 0 3/8 1 tp= 60KHz 0 0 1 2/8 0 0 0 1/8 PROGRAM EXAMPLE:
LDIA OUTA LDIA OUTA LDIA OUTA #1001B ; basic frequency : 60 KHz tone output P30 #0011B ; 600 Hz tone output P24 #0001B P23
RESETTING FUNCTION When CPU in normal working condition and RESET pin holds in low level for three instruction cycles at least, then CPU begins to initialize the whole internal states, and when RESET pin changes to high level, CPU begins to work in normal condition. The CPU internal state during reset condition is as following table : Hardware condition in RESET (f1) state Program counter Status flag Interrupt enable flip-flop ( EI ) MASK0 ,1, 2, 3 Interrupt latch ( IL ) P3, P9, 16, 25, 27, 28, 29, 30 P4, 8, 17, 23, 24 RC oscillator Initial value 0000h 01h 00h 00h 00h 00h 0Fh Start oscillation
The RESET pin is a hysteresis input pin and it has a pull-up resistor available by mask option. The simplest RESET circuit is connect RESET pin with a capacitor to VSS and a diode to VDD.
RESET
* This specification are subject to be changed without notice.
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EM73962A 4-BIT MICROCONTROLLER
EM73962A I/O PORT DESCRIPTION :
Port 0E 1 2 3 4 5 6 7 8E 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Input function Input port , wakeup function -------Input port, wakeup function, external interrupt input -------Output function --P3(1..0) : ROM bank selection ----Output port P9.3 : RAM bank selection ------Sleep/Hold mode control register Sound effect volume control register -----Sound effect frequency register Sound effect command register Timebase control register -LCD control register Timer/counter A control register Timer/counter B control register Sound effect command register -Note
I
E I
I I
I I I I I I I
low nibble high nibble
* This specification are subject to be changed without notice.
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EM73962A 4-BIT MICROCONTROLLER
ABSOLUTE MAXIMUM RATINGS
Items Supply Voltage Input Voltage Output Voltage Power Dissipation Operating Temperature Storage Temperature Sym. VDD VIN VO PD TOPR TSTG Ratings -0.5V to 6V -0.5V to VDD+0.5V -0.5V to VDD+0.5V 300mW 0oC to 50oC -55oC to 125oC Conditions
TOPR=50oC
RECOMMANDED OPERATING CONDITIONS
Items Supply Voltage Input Voltage Operating Frequency Sym. V DD V IH V IL FC Ratings 2.4V to 5.0V 0.90xVDD to VDD 0V to 0.10xVDD 480K to 4MHz Condition
CLK (RC osc)
DC ELECTRICAL CHARACTERISTICS (VDD=30.3V, VSS=0V, TOPR=25oC) Parameters
Supply current
Sym.
I DD
Min.
-
Typ.
0.5 0.1 200 600 15 20
Max. Unit
1 1
0.75VDD 0.4VDD
Conditions
VDD=3.3V, no load, Fc=4MHz (R=91K) VDD=3.3V, sleep mode RESET, P0, P8 P0, RESET, VDD=3.3V, VIH=3.3/0V Open-drain, VDD=3.3V, VIH=3.3/0V Push-pull, VDD=3.3V, VIL=0.4V Push-pull, VDD=2.7V, SOUND, IOH=-0.9mA Push-pull, VDD=2.7V, P8, IOH=-40A VDD=2.7V, IOL=0.9mA Open-drain, VDD=3.3V, VO=3.3V P0 RESET Fc=4MHz, RC osc, [F(3V)-F(2.4V)]/F(3V) Fc=4MHz, VDD=3V, RC osc, [F(typical)-F(worse case)]/F(typical)
mA A V V A A A V V V A K K % %
Hysteresis voltage Input current
V HYS+ V HYSI IH I IL V OH V OL I LO R IN
0.5VDD 0.2VDD
Output voltage
Leakage current Input resistor Frequency stability Frequency variation
2.4 2.0 100 300 -
1 1 -500 0.3 1 300 900 -
* This specification are subject to be changed without notice.
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EM73962A 4-BIT MICROCONTROLLER
(VDD=4.50.5V, VSS=0V, TOPR=25oC) Parameters
Supply current Hysteresis voltage Input current
Sym.
I DD V HYS+ V HYSI IH I IL V OH V OL I LO R IN
Min.
0.5VDD 0.2VDD
Typ.
0.7 0.1 90 300 10 20
Max. Unit
1.5 1
0.75VDD 0.4VDD
Conditions
VDD=5V, no load,Fc=4MHz (R=91K) VDD=5V, sleep mode RESET, P0, P8 P0, RESET, VDD=5V,VIH=5/0V Open-drain, VDD=5V,VIH=5/0V Push-pull, VDD=5V ,VIL=0.4V Push-pull, SOUND, VDD=4V, IOH=-4mA Push-pull, P8, VDD=4V, IOH=-200A VDD=4V, IOL=4mA Open-drain, VDD=5V, VO=5V P0 RESET Fc=4MHz,RC osc,[F(4.5V)-F(3.6V)]/F(4.5V) Fc=4MHz, VDD=4.5V, RC osc, [F(typical)-F(worse case)]/F(typical)
Output voltage
Leakage current Input resistor Frequency stability Frequency variation
3.0 2.4 30 100 -
1 1 -1 1.0 1 150 450 -
mA A V V A A mA V V V A K K % %
* This specification are subject to be changed without notice.
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EM73962A 4-BIT MICROCONTROLLER
RESET PIN TYPE
TYPE RESET-A
RESET
mask option
OSCILLATION PIN TYPE
TYPE OSC-C
CLK
RC Osc. (comparator)
INPUT PIN TYPE
TYPE INPUT-A TYPE INPUT-B
WAKEUP function mask option
: mask option
P0/WAKEUP
TYPE INPUT-A
I/O PIN TYPE
TYPE I/O TYPE I/O-L
path B path A
mask option Output data latch SEL
Special function control input Input data Output data
TYPE I/O
WAKEUP function mask option
* This specification are subject to be changed without notice.
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EM73962A 4-BIT MICROCONTROLLER
TYPE I/O-N
TYPE I/O-O
path B path A Input data
TYPE I/O-N
Output data latch
Output data Special function output
: mask option
: mask option
Path A : Path B :
For set and clear bit of port instructions, data goes through path A from output data latch to CPU. For input and test instructions, data from output pin go through path B to CPU and the output data latch will be set to high.
* This specification are subject to be changed without notice.
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EM73962A 4-BIT MICROCONTROLLER APPLICATION CIRCUIT
VBAT
VBAT 0.1F
VDD
3V/4.5V
P0.0 P0.1 P0.2 P0.3 TEST SOUND
SEG0~ SEG39 COM0~ COM7
LCD PANNEL 40 x 8 dots 1/8 duty 1/4 or1/5 bias
Buzzer
VDD
RESET
0.1F RESET
CLK
VSS
EM73962A
* This specification are subject to be changed without notice.
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EM73962A 4-BIT MICROCONTROLLER
PAD DIAGRAM
TEST SEG0 SEG1 SEG2 SEG3 VSS P0.3 P0.2 P0.1 P0.0 P8.3 P8.2 P8.1 P8.0
62 RESET CLK VDD SOUND COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 SEG39 SEG38 SEG37 SEG36 SEG35 1 2 3 4 5 6 7 8
61
60
59
58
57
56
55
54
53
52
51
50
49 48 47 46 45 44 43 42 41 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20
(0,0) 9 10 11 12 13 14 15 16 17
ELAN
40 39 38 37
EM73962A
36 35 34 33 32
18
SEG34
19
SEG33
20
SEG32
21
SEG31
22
SEG30
23
SEG29
24
SEG28
25
SEG27
26
SEG26
27
SEG25
28
SEG24
29
SEG23
30
SEG22
31
SEG21
Chip Size : 1740 x 2460 m Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Symbol RESET CLK VDD SOUND COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 X -702.7 -702.7 -702.7 -702.7 -702.7 -702.7 -702.7 -702.7 -702.7 -702.7 -702.7 -702.7 -702.7 -702.7 -702.7 -702.7 -702.7 -728.0 Y 891.1 780.7 658.4 540.7 430.2 319.7 209.3 98.8 -11.6 -122.1 -232.6 -343.0 -453.5 -563.9 -674.4 -784.9 -895.3 -1062.8
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* This specification are subject to be changed without notice.
EM73962A 4-BIT MICROCONTROLLER
Pad No. 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 Unit : m
Symbol SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 VSS P8.0 P8.1 P8.2 P8.3 P0.0 P0.1 P0.2 P0.3 TEST
X -617.6 -507.1 -396.6 -286.2 -175.7 -65.3 45.2 155.7 266.1 376.6 487.0 597.5 708.0 700.4 700.4 700.4 700.4 700.4 700.4 700.4 700.4 700.4 700.4 700.4 700.4 700.4 700.4 700.4 700.4 700.4 724.6 614.1 503.7 393.2 269.3 145.8 35.4 -75.1 -185.6 -296.0 -406.5 -516.9 -627.4 -737.9
Y -1062.8 -1062.8 -1062.8 -1062.8 -1062.8 -1062.8 -1062.8 -1062.8 -1062.8 -1062.8 -1062.8 -1062.8 -1062.8 -877.7 -767.3 -656.8 -546.3 -435.9 -325.4 -215.0 -104.5 6.0 116.4 226.9 337.3 447.8 558.3 668.7 779.2 889.6 1062.2 1062.2 1062.2 1062.2 1062.2 1062.2 1062.2 1062.2 1062.2 1062.2 1062.2 1062.2 1062.2 1062.2
For PCB layout, IC substrate must be floated or connected to Vss.
* This specification are subject to be changed without notice.
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EM73962A 4-BIT MICROCONTROLLER
INSTRUCTION TABLE
(1) Data Transfer Mnemonic LDA x LDAM LDAX LDAXI LDH #k LDHL x LDIA #k LDL #k STA x STAM STAMD STAMI STD #k,y STDMI #k THA TLA (2) Rotate Mnemonic RLCA RRCA Object code ( binary ) 0101 0000 0101 0001 Operation description CFAcc CFAcc Byte 1 1 Cycle 1 1 C C C Flag Z Z Z Object code ( binary ) 0110 1010 xxxx xxxx 0101 1010 0110 0101 0110 0111 1001 kkkk 0100 1110 xxxx xx00 1101 kkkk 1000 kkkk 0110 1001 xxxx xxxx 0101 1001 0111 1101 0111 1111 0100 1000 kkkk yyyy 1010 kkkk 0111 0110 0111 0100 Operation description AccRAM[x] Acc RAM[HL] AccROM[DP]L AccROM[DP]H,DP+1 HRk LRRAM[x],HRRAM[x+1] Acck LRk RAM[x]Acc RAM[HL]Acc RAM[HL]Acc, LR-1 RAM[HL]Acc, LR+1 RAM[y]k RAM[HL]k, LR+1 AccHR AccLR Byte 2 1 1 1 1 2 1 1 2 1 1 1 2 1 1 1 Cycle 2 1 2 2 1 2 1 1 2 1 1 1 2 1 1 1 C Flag Z Z Z Z Z Z Z Z Z Z Z
S 1 1 1 1 1 1 1 1 1 1 C C' 1 C' 1 1
S C' C'
(3) Arithmetic operation 3) Mnemonic ADCAM ADD #k,y ADDA #k ADDAM ADDH #k ADDL #k ADDM #k DECA DECL DECM INCA Object code ( binary ) 0111 0100 0110 0111 0110 0110 0110 0101 0111 0101 0101 0000 1001 kkkk yyyy 1110 0101 kkkk 0001 1110 1001 kkkk 1110 0001 kkkk 1110 1101 kkkk 1100 1100 1101 1110 Operation description AccAcc + RAM[HL] + CF RAM[y]RAM[y] +k AccAcc+k AccAcc + RAM[HL] HRHR+k LRLR+k RAM[HL]RAM[HL] +k AccAcc-1 LRLR-1 RAM[HL]RAM[HL] -1 AccAcc + 1 Byte 1 2 2 1 2 2 2 1 1 1 1 Cycle 1 2 2 1 2 2 2 1 1 1 1 C C Flag Z Z Z Z Z Z Z Z Z Z Z Z
S C' C' C' C' C' C' C' C C C C'
* This specification are subject to be changed without notice.
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EM73962A 4-BIT MICROCONTROLLER
INCL INCM SUBA #k SBCAM SUBM #k
0111 1110 0101 1111 0110 1110 0111 kkkk 0111 0010 0110 1110 1111 kkkk
LRLR + 1 RAM[HL]RAM[HL]+1 Acck-Acc AccRAM[HLl - Acc - CF' RAM[HL]k - RAM[HL]
1 1 2 1 2
1 1 2 1 2
C -
Z Z Z Z Z
C' C' C C C
(4) Logical operation
Mnemonic ANDA #k ANDAM ANDM #k ORA #k ORAM ORM #k XORAM (5) Exchange Mnemonic Object code ( binary ) Operation description Byte Cycle Flag C Z Object code ( binary ) Operation description 0110 0111 0110 0110 0111 0110 0111 1110 0110 kkkk 1011 1110 1110 kkkk 1110 0100 kkkk 1000 1110 1100 kkkk 1001 AccAcc&k AccAcc & RAM[HL] RAM[HL]RAM[HL]&k AccAcc k Acc Acc RAM[HL] RAM[HL]RAM[HL] k AccAcc^RAM[HL]
-----
Byte 2 1 2 2 1 2 1
Cycle 2 1 2 2 1 2 1 C -
Flag Z Z Z Z Z Z Z Z
S Z' Z' Z' Z' Z' Z' Z'
S
EXA x EXAH EXAL EXAM EXHL x
0110 1000 xxxx xxxx 0110 0110 0110 0100 0101 1000 0100 1100 xxxx xx00
AccRAM[x] AccHR AccLR AccRAM[HL] LRRAM[x], HRRAM[x+1]
2 1 1 1 2
2 2 2 1 2
-
Z Z Z Z -
1 1 1 1 1
(6) Branch
Mnemonic Object code ( binary ) Operation description Byte Cycle Flag C Z
S
SBR a LBR a SLBR a
00aa aaaa 1100 aaaa aaaa aaaa 0101 0101 1100 aaaa
aaaa aaaa (a:1000~1FFFh)
If SF=1 then PCPC12-6.a5-0 elsenull If SF= 1 then PCa else null If SF=1 then PCa else null
1 2 3
1 2 3
-
-
1 1 1
0101 0111 1100 aaaa
aaaa aaaa (a:0000~0FFFh)
(7) Compare
Mnemonic Object code ( binary ) Operation description Byte Cycle Flag C Z
S
CMP #k,y 0100 1011 kkkk yyyy CMPA x 0110 1011 xxxx xxxx
k-RAM[y] RAM[x]-Acc
2 2
2 2
C C
Z Z
Z' Z'
32
* This specification are subject to be changed without notice.
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EM73962A 4-BIT MICROCONTROLLER
Mnemonic
Object code ( binary )
Operation description
Byte
Cycle C
Flag Z
S
CMPAM CMPH #k CMPIA #k CMPL #k
0111 0011 0110 1110 1011 kkkk 1011 kkkk 0110 1110 0011 kkkk
RAM[HL] - Acc k - HR k - Acc k-LR
1 2 1 2
1 2 1 2
C C -
Z Z Z Z
Z' C Z' C
(8) Bit manipulation Mnemonic CLM CLP CLPL CLR SEM SEP SEPL SET TF TFA TFM TFP TFPL TT TTP b p,b y,b b p,b y,b y,b b b p,b y,b p,b Object code ( binary ) 1111 00bb 0110 1101 11bb pppp 0110 0000 0110 1100 11bb yyyy 1111 01bb 0110 1101 01bb pppp 0110 0010 0110 1100 01bb yyyy 0110 1100 00bb yyyy 1111 10bb 1111 11bb 0110 1101 00bb pppp 0110 0001 0110 1100 10bb yyyy 0110 1101 10bb pppp Operation description RAM[HL]b0 PORT[p]b0 PORT[LR3-2+4]LR1-00 RAM[y]b0 RAM[HL]b1 PORT[p]b1 PORT[LR3-2+4]LRl-01 RAM[y]b1 SFRAM[y]b' SFAccb' SFRAM[HL]b' SFPORT[p]b' SFPORT[LR 3-2 +4]LR1-0' SFRAM[y]b SFPORT[p]b Byte 1 2 1 2 1 2 1 2 2 1 1 2 1 2 2 Cycle 1 2 2 2 1 2 2 2 2 1 1 2 2 2 2 C Flag Z -
S 1 1 1 1 1 1 1 1 * * * * * * *
(9) Subroutine Mnemonic LCALL a SCALL a Object code ( binary ) 0100 0aaa aaaa aaaa 1110 nnnn Operation description STACK[SP]PC, SPSP -1, PCa STACK[SP]PC, SPSP - 1, PCa, a = 8n + 6 (n =115),0086h (n = 0) SPSP + 1, PCSTACK[SP] Byte 2 1 Cycle 2 2 Flag Z C -
S -
RET (10) Input/output Mnemonic INA INM OUT OUTA OUTM p p #k,p p p
0100 1111
1
2
-
-
-
Object code ( binary ) 0110 1111 0100 pppp 0110 1111 1100 pppp 0100 1010 kkkk pppp 0110 1111 000p pppp 0110 1111 100p pppp
Operation description AccPORT[p] RAM[HL]PORT[p] PORT[p]k PORT[p]Acc PORT[p]RAM[HL]
Byte 2 2 2 2 2
Cycle 2 2 2 2 2 C -
Flag Z Z -
S Z' Z' 1 1 1
33
* This specification are subject to be changed without notice.
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EM73962A 4-BIT MICROCONTROLLER
(11) Flag manipulation Mnemonic TFCFC TTCFS TZS Object code ( binary ) Operation description 0101 0011 0101 0010 0101 1011 SFCF', CF0 SFCF, CF1 SFZF Byte 1 1 1 Cycle 1 1 1 C 0 1 Flag Z S * * *
(12) Interrupt control Mnemonic CIL r DICIL r EICIL r EXAE RTI Object code ( binary ) Operation description 0110 0011 11rr rrrr 0110 0011 10rr rrrr 0110 0011 01rr rrrr 0111 0101 0100 1101 ILIL & r EIF0,ILIL&r EIF1,ILIL&r MASKAcc SPSP+1,FLAG.PC STACK[SP],EIF 1 Byte 2 2 2 1 1 Cycle 2 2 2 1 2 C * Flag Z *
S 1 1 1 1 *
(13) CPU control Mnemonic NOP Object code ( binary ) 0101 0110 Operation description no operation Byte 1 Cycle 1 C Flag Z -
S -
(14) Timer/Counter & Data pointer & Stack pointer control Mnemonic LDADPL LDADPM LDADPH LDASP LDATAL LDATAM LDATAH LDATBL LDATBM LDATBH STADPL STADPM STADPH STASP STATAL STATAM STATAH STATBL STATBM STATBH Object code ( binary ) 0110 1010 1111 1100 0110 1010 1111 1101 0110 1010 1111 1110 0110 1010 1111 1111 0110 1010 1111 0100 0110 1010 1111 0101 0110 1010 1111 0110 0110 1010 1111 1000 0110 1010 1111 1001 0110 1010 1111 1010 0110 1001 1111 1100 0110 1001 1111 1101 0110 1001 1111 1110 0110 1001 1111 1111 0110 1001 1111 0100 0110 1001 1111 0101 0110 1001 1111 0110 0110 1001 1111 1000 0110 1001 1111 1001 0110 1001 1111 1010 Operation description Acc[DP] L Acc[DP] M Acc[DP] H AccSP Acc[TA] L Acc[TA]M Acc[TA]H Acc[TB] L Acc[TB]M Acc[TB]H [DP] LAcc [DP] MAcc [DP] HAcc SPAcc [TA] LAcc [TA] MAcc [TA] HAcc [ TB]LAcc [TB] MAcc [TB] HAcc Byte 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Cycle 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 C Flag Z Z Z Z Z Z Z Z Z Z Z -
S 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
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* This specification are subject to be changed without notice.
10.8.2001
EM73962A 4-BIT MICROCONTROLLER
**** SYMBOL DESCRIPTION
Symbol HR PC SP ACC CF SF IL PORT[p] RAM[x] ROM[DP]H [DP]M [TA]L([TB]L) [TA]H([TB]H) LR3-2 PC12-6 --
Description H register Program counter Stack pointer Accumulator Carry flag Status flag Interrupt latch Port ( address : p ) Timer/counter B Data memory (address : x ) High 4-bit of program memory Middle 4-bit of data pointer register Low 4-bit of timer/counter A (timer/counter B) register High 4-bit of timer/counter A (timer/counter B) register Bit 3 to 2 of LR Bit 12 to 6 of program counter Exchange Substraction Logic OR Inverse operation 4-bit immediate data 4-bit zero-page address Bit address
Symbol LR DP STACK[SP] FLAG ZF EI MASK RAM[HL] ROM[DP]L [DP]L [DP]H [TA]M([TB]M) LR 1-0 a5-0 + & ^ . x p r
Description L register Data pointer Stack specified by SP All flags Zero flag Enable interrupt register Interrupt mask Timer/counter A Data memory (address : HL ) Low 4-bit of program memory Low 4-bit of data pointer register High 4-bit of data pointer register Middle 4-bit of timer/counter A (timer/counter B) register Contents of bit assigned by bit 1 to 0 of LR Bit 5 to 0 of destination address for branch instruction Transfer Addition Logic AND Logic XOR Concatenation 8-bit RAM address 4-bit or 5-bit port address 6-bit interrupt latch
#k y b
* This specification are subject to be changed without notice.
10.8.2001
35

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